Controlling power consumption has become an important design challenge in modern integrated circuit (IC) devices, such as in programmable logic devices (PLDs) and standard cell application specific integrated circuits (ASICs). PLDs exist as a well-known type of IC that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An example FPGA includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). CLBs contain look-up tables (LUTs) which are small memories with K inputs capable of implementing any logic function having up to K variables. The CLBs and IOBs are interconnected by a programmable interconnect structure (routing resources). The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, although other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A conventional design process for an integrated circuit, such as an ASIC or an FPGA, begins with the creation of the design. The design specifies the function of a circuit at a schematic or logic level and may be represented using various programmable languages (e.g., VHDL, ABEL or Verilog) or schematic capture programs. The design is synthesized to produce a logical network list (“netlist”) supported by the target integrated circuit device. The synthesized design is mapped onto primitive components within the target device (e.g., programmable logic blocks of an FPGA). Placement of the components of the synthesized and mapped design is then performed for the target device. Interconnects (e.g., signal conductors) are routed within the target device for the placed components.
Performance and frequency requirements translate to a maximum allowable delay for paths traversing routing resources between circuit elements. As such, the conventional design process is “timing-driven” in that the process is optimized in accordance with timing constraints. Oftentimes a timing-driven optimization process does not optimize the design for power consumption. In some instances, incorporating power optimization in the conventional design process may adversely affect the timing performance of the design.
A few post-routing power optimization techniques have been explored, but such techniques are often inefficient and require significant computing power and offer less than desirable power savings. Other problems arise due to variable circuit and LUT sizes.
Accordingly, there exists a need in the art for an integrated circuit design process that addresses these and other problems in power optimization including an efficient method that does not adversely affecting the timing performance of the design.